LPC1343 USB Bootloader

Monday, December 28, 2009

The first prototypes for the 1343 Reference Design came in this morning, and we put two of them together to test.  Everything looks to be OK, but the only real question mark was the USB interface ... which thankfully seems to be the same as what's found on many ARM7 chips like the LPC2148.  We had previously mentionned that the LPC1343 includes a built-in USB bootloader that allows you to enumerate the board as a Mass Storage Device, in addition to the classic UART-based ISP.  With the USB bootloader you can simply drag and drop your compiled binary file onto the device as you would with any USB flash drive, and it will update itself accordingly.  No more messing around with FlashMagic, which is nice, but more importantly this significantly lowers the barrier for updating devices in the field if you don't want to implement your own custom in-application programming code.  (For reference sake, you can control whether the drive that appears is write-only, or whether the firmware can be both read/written on the device.)

We've designed the 1343 reference board so that if you have a USB cable plugged in when you enter ISP mode, it will automatically select the USB bootloader.  If a USB cable is not connected when you enter ISP mode, the classic UART-based interface will be enabled, allowing you to update your device using FlashMagic (or any comparable software).  You can see a screenshot below of the 1343 enumerating as a Mass Storage Device:

LPC1343 USB Bootloader Enumeration

The newly enumerated mass storage device will have the same size as the flash on the chip, which is 32KB in the case of the LPC1343:

LPC1343 USB Bootloader - Device Properties

Given the convenience of the new USB bootloader, we've made some changes to the LPC1343 Reference Design to make accessing ISP mode as easy as possible.  Rather than setting an ISP jumper, resetting the device with the reset button, and then going into ISP mode we've add a single 'bootloader' button that when pressed will reset the device and automatically go into ISP-mode (whether USB or UART-based).  We should get the new prototypes back in a week or so, but if everything looks alright we'll update the schematics and probably put together an initial batch of fully assembled boards.

While the new USB bootloader isn't a life-changing addition, it's definately a little detail that goes a long way to making the LPC1343 (and presumably any new USB-enabled devices in the same Cortex M3 family) easier to use, with less time and effort involved on the developpment side for people working with these chips!

Note for LPCXpresso Users: There is a bug in version 3.1 or lower of LPCXpresso that adds the incorrect checksum to binary files. We've made a blog post with a quick work-around for this until Code Red puts out an updated version of their conversion utility: Creating Valid LPC1343 Binaries in LPCXpresso.

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Connecting Segger J-Link to Cortex M0/M3 SWD

Tuesday, December 22, 2009

While the latest revision of Segger's J-Link for ARM fully supports both SWD and SWO, it doesn't include a cable to match the new 2x05 pin 0.05" connector that has been settled upon as the standard (replacing the much larger JTAG 20 pin 0.1" Molex-type connector found on ARM7 and ARM9 development boards).  As such, you'll need to find a way to connect it to your board if you want to do any sort of debugging.  In the case of our Cortex M0 LPC1114 and Cortex M3 LPC1343 boards, we've decided to include two identically wired SWD connectors on the PCB in both 0.05" and 0.1" pitch to make connecting non-0.05" devices easier.

While a full interface description for the J-Link is available on Segger's website, for convenience sake we've reproduced the pin layout here as well.  You simply need to connect the J-Link to the on-board 0.1" SWD connector using standard jumper wire (though we may make a simple adapter board if there is enough interest):

Segger J-Link to SWD Pinout
J-Link SWD Connector Description
1 - VTref 1 - VCC J-Link Target Reference Voltage
4 - GND 9 - GNDDetect GND connection (J-Link 6, 8, 10, 12, 14, 16, 18 or 20 can also be used)
7 - SWDIO 2 - SWDIO SWD I/O
9 - SWCLK 4 - SWCLK SWD Clock Signal
13 - SWO 6 - SWO Serial Wire Output trace port (optional)
15 - RESET 10 - nReset Reset pin
Keil provides an excellent overview of the various JTAG and SWD connectors as well as pinout diagrams here: Target Connectors

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Building Intel Hex Files with LPCXpresso

Wednesday, December 16, 2009

We've been trying to test out the new LPCXpresso IDE (essentially a free, 128KB-limited version of Code Red's Red Suite) and our own LPC1114 Reference Design, but since we haven't yet set up a 32-bit development environment to be able to make use of the LPC-Link built into the LPCXpresso boards (there are no 64-bit drivers available yet) we were just going to fallback to good old-fashion FlashMagic, and upload the compiled hex files via ISP.  Unfortunately, that meant that we needed a good old-fashion Intel hex file as well!

While LPCXpresso can generate Intel hex files, you need to make a small adjustment to the project settings to do so:

  1. Right-click on your project in the Project Explorer window, and select Properties from the pop-up menu.
  2. Expand C/C++ Build on the left-hand side of the Properties dialogue, and select Settings.
  3. In Settings, switch to the Build Steps tab, and you should see a screen similar to the this:
    Configuring LPCXpresso to build Intel hex files
  4. The post-build command to generate an Intel hex file is already present (at least in v3.1 of LPCXpresso), but it is commented out.  You need to replace the text in Post-build steps / Command as follows:
Original Text
arm-none-eabi-size ${BuildArtifactFileName}; # arm-none-eabi-objcopy -O ihex ${BuildArtifactFileName} ${BuildArtifactFileBaseName}.hex ;
Replacement Text
arm-none-eabi-size ${BuildArtifactFileName}; arm-none-eabi-objcopy -O ihex ${BuildArtifactFileName} ${BuildArtifactFileBaseName}.hex ;

After that, build your project as normal and a .hex file should also be generated in the build folder (for example, /Debug). Please note that you will need to make the same change to both the Debug and Release configurations if you wish to generate Intel hex files for both build types.

For more information on configuring the build output for Code Red, you might want to have a look at Generating srec (Motorola S format), binary, ihex (Intel Hex) files on the Code Red wiki.

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LPC1343 Reference Design

Tuesday, December 15, 2009

We just finished routing our first attempt at an LPC1343 Reference Design (Cortex M3 core), and the boards should be back in two weeks time.  We had originally planned on releasing an LPC1313 board, but the 1343 seems to be a much more appropriate choice in that it not only has USB 2.0 support (unlike the comparable LPC2103 in ARM7 or LPC1114 in Cortex M0 which we also have reference designs available for), but it has HID and Mass Storage support built right into the ROM.  The main advantage of this isn't so much convenience (though that's a nice bonus), but that you're able to save valuable flash and SRAM since you don't have to add in your own USB stack.  On a 32KB/8KB part, every byte makes a difference, and in this case you're probably saving at least 2-3KB!

The LPC1343 is very similar to the LPC1114, so there shouldn't be any surprises when we get the boards back, but we did make a number of changes based on our experience with the LPC1114.  Solder jumpers were added to allow someone to physically disconnect the external crystal (to save power if you're only using the internal oscillator, or just want to be 100% sure you're NOT using the external crystal). LPC1343 Reference Design (Prototype)We previously had physical 0.1" jumpers on the LPC1114 prototype, and it seemed wasteful to have the jumpers sticking up off the board when you're only likely to change their state once or twice anyway.  Unlike the LPC1114 board -- which was designed to be battery powered -- the LPC1343 board can only be powered from either USB or a 2.0/2.1mm DC barrel.  There is no step-up converter included on the board.  We also decided to use only 0805 components (rather than the 0603 parts that we typically use) simply to make it a bit easier for someone to hand-populate the board or solder it by hand if required.  Other than that, the main wiring on the board is very similar, and the 1343 seems to be more or less pin-compatible with the 1114.

Similar to the LPC1114 board, we've also included two (identically wired) SWD connectors: the standard ten pin 0.05" SMT connector, along with a larger 0.1" 10-pin Molex-type connector to allow you to more easily connect hardware debuggers that don't have the new 0.05" cable (currently Keil is the only company providing a hardware debugger with the new connectors on it).  You can easily hook a Segger J-Link up to the board using some jumper wires, for example.

In any case, we"ll post an update once the boards are in, and will put the Eagle files and schematics up once we're convinced that the basic design is sound.  It's a great time to be developping hardware, as feature sets go up, prices go down, and everything seems to get easier than it was before!

Update: A nice feature on the LPC1343 that's easy to miss at first glance is that it has a built in USB Bootloader as well as the classic UART-based ISP. When you boot the device into ISP mode (by setting P0.1 LOW after reset), the bootloader will check the state of pin 0.3. If P0.3 is HIGH, it will cause the LPC1343 to enumerate as a USB/MSC device and will appear as a filesystem on Windows/Linux PCs; If P0.3 is LOW, it will boot into the classic UART/ISP mode and you can update the device using FlashMagic. (For reference sake, we've designed the board to boot into USB mode when the ISP jumper is set and a USB cable is connected, but it will fall back to the the classic UART/ISP mode when a USB cable is not connected.)

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